In order to reduce dynamic and static power consumption on leaky processes, devices implement dynamic voltage and frequency scaling to adapt energy to the required performance. Voltage and frequency changes impact system behavior and should be properly managed. For example, voltage and frequency changes impact delay-locked loops (DLLs) used in interfaces such as memory controllers by causing loss of lock of the delay-locked loops (DLLs) so that on-going accesses to devices such as memory may be corrupted. For conventional devices to continue to process properly during frequency transitions requires heavy and undesirable software management, for example. Performing dynamical voltage and frequency scaling (DVFS) conventionally on an interface such as a memory controller causes the delay-locked loop (DLL) or any equivalent delay control cell, used, for example, to manage an external double data rate (DDR) memory, to lose its lock and, therefore, corrupt memory accesses. Conventionally, dynamic voltage and frequency scaling (DVFS) is only applied on processors.
In order to optimize multi-processor devices and uni-processor, multi-core processor devices, a multiple asynchronous clock domain architecture is implemented. Each of the multiple asynchronous clock domains may potentially be supplied by a dedicated digital phase-locked loop (DPLL) to match the various frequency requirements. However, each of the digital phase-locked loops (DPLLs) in each of the asynchronous clock domains generates a high speed synthesized clock and has a significant dynamic power consumption. Furthermore, when a new synthesized frequency value is programmed on a given digital phase-locked loop (DPLL), for example, in a dynamic voltage and frequency scaling (DVFS) context, processing performance is negatively impacted during the digital phase-locked loop (DPLL) re-lock operation.